1. Field of Invention
This invention relates to providing isolation between transistors of semiconductor devices and in particular to a process for making semiconductor devices having such isolation wherein the semiconductor device is planarized.
2. Background of the Invention
Various ways have been proposed to electrically isolate a plurality of pockets of semiconductor material in which one or more circuit elements can be formed. For example, these pockets can be isolated by growing oxide in certain regions of the silicon wafer. This is called local oxidation. This local oxidation produces a nonplanar surface because when silicon oxide is grown on the surface of silicon the thickness of the oxide which grows is approximately twice the thickness of the silicon oxidized. If a silicon surface is not etched prior to oxidation, the so called semi-recessed oxide results. If the silicon surface is etched prior to oxidation, the so called fully-recessed isolation results. Both the semi-recessed and the fully-recessed oxides suffer from lateral encroachment or growth of the isolation region. This is called "birds beaks" and it tends to occur at the boundary between the oxide being grown and the silicon. It can occur due to an extension of the growing oxide underneath a mask due to lateral diffusion of the oxidizing species.
When the semi-recessed oxide grows to a level higher than the original silicon surface, a nonplanar surface results. The fully-recessed oxide is flush with the original surface in large areas, but there are local ridges or "birds heads" at the edges. These must be planarized to avoid ribbon formation. Semi-recessed isolation is usually used for MOS technologies, while a planarized fully-recessed technology is used for bipolar circuits.
Encroachment reduces the area available to build devices on a wafer. To avoid encroachment, isolation schemes have been suggested which involve etching shallow trenches into the silicon surface, depositing oxide by chemical vapor deposition over the surface of the wafer, and then planarizing the surface by an elaborate combination of photolithography and reactive-ion-etching.
Many other ways have also been proposed to provide electrical isolation between circuit elements. Among the ways proposed are biased PN junctions disclosed in U.S. Pat. No. 3,117,260, issued Noyce on Jan. 7, 1964; combinations of PN junctions and zones of intrinsic and extrinsic semiconductor materials as taught in the U.S. patent issued to Noyce on Sept. 22, 1964; dielectric isolation disclosed in U.S. Pat. No. 3,391,023, issued to Frescura on July 2, 1968; and mesa etching disclosed in U.S. Pat. No. 3,489,961, issued to Frescura Jan. 13, 1970. Tucker, et al., in application Ser. No. 845,822, filed July 29, 1969, discloses the use of selectively doped polycrystalline silicon to help isolate islands of single crystal silicon in which circuit elements can be formed.
After electrically isolated pockets of semiconductor material are prepared, active and passive circuit elements are formed within or on the pockets. Many of these circuit elements are typically formed using the planar diffusion techniques disclosed by Hoerni in U.S. Pat. Nos. 3,025,589 and 3,064,167. In the planar process, the regions of each semiconductor pocket into which circuit elements are diffused are controlled by forming a diffusion mass from an insulation layer formed on the surface of the semiconductor material. After the desired elements have been formed in the semiconductor material, a conductive lead pattern is formed on the insulation and used to interconnect selective active and passive circuit elements into the desired circuit. Additional passive circuit elements can also be formed on the insulation and interconnected into the circuit. Such a structure is disclosed in U.S. Pat. No. 2,981,877, issued to Noyce on Apr. 25, 1961. Another way to improve planarization and reduce encroachment with grown oxide techniques is to change materials in the masking layer and put a layer of polysilicon between the oxide and the nitride.
In the manufacture of integrated circuits, several problems arise. First, the area of the wafer required for the placement of the isolation regions between adjacent pockets of semiconductor material is a significant portion of the total wafer area. A large isolation area reduces the number of devices which can be placed in a wafer and thus lowers the packing density of the circuit elements formed in the wafer. Second, the leads formed on, and adherent to, the insulation on the wafer surface sometimes crack at steps in the insulation on the wafer surface. These steps are often quite steep. To eliminate cracks in the interconnect leads at steps in the insulation, J. S. Sa in U.S. Pat. No. 3,404,451, issued Oct. 8, 1968, disclosed removing portions of this insulation from the wafer surface during processing. It has also been proposed to slope the edges of the insulation at the contact window. Another approach is to etch grooves into the semiconductor wafer adjacent to those regions in which PN junctions are formed and thermally oxidizing the material exposed by the grooves.
Third, several of the isolation techniques result in significant capacitances being introduced into the integrated circuit. At low frequencies, these capacitances do not affect the operation of the circuit. However, at high frequences these capacitances can have a significant effect on circuit performance.
Shallow trench isolation technology using RIE, CVD oxide fill and planarization to realize lithography-limited, submicron device and isolation dimensions is taught in "A Variable-Size Shallow Trench Isolation (STI) Technology with Defused Sidewall Doping for Submicron CMOS" by B. Davari, IEEE publication number CH2528-8/88/0000-0092, proceedings 1988 IEDM Conference, San Francisco, Calif. In this method, in order to achieve planarization, the trenches are filled with CVD oxide after passivation of the sidewalls by a boron diffusion. A block resist is then patterned followed by a planarization resist coat. The CVO oxide and the resist are then etched back and the surface is planarized. However, in addition to requiring the etchback, this method requires an extra photomasking step to pattern the blocking resist layer. This is expensive and a source of defects. This is required because a single planarization resist coat does not provide good results in the presence of large high or low areas.